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 | | Re: loading s/w
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| (...) That's what I am doing. Markus. (25 years ago, 21-Apr-99, to lugnet.robotics.rcx.legos)
| | | | | Re: legOS Network Protocol
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| (...) Hmm.. with a little hacking you could certainly detect logic errors. The main problem I think would be writing alternative C-Functions for the H8 assembler, which makes up legOS itself. You'd also need to create a simulator engine for legOS to (...) (25 years ago, 21-Apr-99, to lugnet.robotics.rcx.legos)
| | | | | Re: loading s/w
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| (...) The first instruction (at 03ae) places the stack in on-chip memory, assuming RAME bit of SYSCR is at its initial value of 1. Why not make rom_reset() disable interrupts, then do its thing? That would be the safest thing to do. -Kekoa (25 years ago, 21-Apr-99, to lugnet.robotics.rcx.legos)
| | | | | Re: loading s/w
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| (...) Well, if rom_reset() gets invoked near the end of your time slice, ROM has no time to reset the OCIA IRQ vector before the next timer tick. I'm not certain about the order in which ROM sets up data areas and IRQ vectors. legOS freely allocates (...) (25 years ago, 20-Apr-99, to lugnet.robotics.rcx.legos)
| | | | | Re: legOS Network Protocol
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| (...) Assuming packets without large internal gaps, we could employ a timeout to wait for a packet transmission of unknown protocol type to end. At 2400 bps with 8E1 (LEGO, isn't it?), one data byte has 11 bits, so a space of 1.5*11/2400 s should be (...) (25 years ago, 20-Apr-99, to lugnet.robotics.rcx.legos)
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