 | | Re: loading s/w —Markus L. Noga
| | | | (...) Well, if rom_reset() gets invoked near the end of your time slice, ROM has no time to reset the OCIA IRQ vector before the next timer tick. I'm not certain about the order in which ROM sets up data areas and IRQ vectors. legOS freely allocates (...) (26 years ago, 20-Apr-99, to lugnet.robotics.rcx.legos)
| | | | | | | | | | Re: loading s/w —Kekoa Proudfoot
| | | | | (...) The first instruction (at 03ae) places the stack in on-chip memory, assuming RAME bit of SYSCR is at its initial value of 1. Why not make rom_reset() disable interrupts, then do its thing? That would be the safest thing to do. -Kekoa (26 years ago, 21-Apr-99, to lugnet.robotics.rcx.legos)
| | | | | | | | | | | | Re: loading s/w —Markus L. Noga
| | | | | (...) That's what I am doing. Markus. (26 years ago, 21-Apr-99, to lugnet.robotics.rcx.legos)
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