Subject:
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Re: mindstorms NXT and memory
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Newsgroups:
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lugnet.robotics
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Date:
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Tue, 10 Jan 2006 17:09:27 GMT
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Viewed:
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10348 times
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In lugnet.robotics, Kevin L. Clague wrote:
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I think that the fact that X86 has effectively gone RISC indicates that RISC
is winning the conceptual battle. You trade a little bit of programming
effort spread across a lot of programmers, for the ability to toss out a lot
of hardware complexity and the engineering cost that it takes to make sure
the complexity is really working.
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I totally agree! I stated this in another thread (or maybe this one) that
assembly code on Intel is like Java Byte Code (but worse). I mean its not like
you *really* know as a “high-level assembly programmer” exactly the order in
which micro-ops were executed.
If your a compiler guy (I know two guys who were at one point heavily involved
with gcc), developing for Intel is a nightmare (how do you know the following
set of instructions doesn’t cause an unneccessary stall 20 stages in the pipe,
etc.).
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Sun’s most recent hardware announcement was for a four stage instruction
pipeline that chip vs chip dramatically outperforms anything Intel (3X) has
(with their 20+ stage pipeline). Now that we’re this far off topic, maybe we
need to move this thread ;^)
It is fun to discuss, but doesn’t really have much to do with NXT so I’ll sit
down and be quiet.
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Sure thing but Kevin this has been a fun discussion to say the least! (and a
good review for me)
-aps
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Message is in Reply To:
 | | Re: mindstorms NXT and memory
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| (...) Now you're talkin! I've never really done more than a half dozen instructions, unless it was a homework problem waaaaaaaay (and I really mean waaaaaaaay ;^) back in college. (...) I guess this is what CISC proponents say. I don't know that I (...) (19 years ago, 10-Jan-06, to lugnet.robotics, FTX)
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